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IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 ( WE Controlled Timing) (1,5)
t WC
ADDRESS
CS 2
CS 1
WE
t AS
t AW
t WR1(2)
DATA OUT
DATA IN
(3)
t WHZ (6)
t WP (5)
t DW
DATA VALID
t OW(6)
t DH1,2
2967 drw 08
Timing Waveform of Write Cycle No. 2 ( CS Controlled Timing) (1)
t WC
ADDRESS
CS 2
t AS
t CW
t WR2(2)
t WR1(2)
CS 1
(4)
t AW
WE
t DW
t DH1,2
DATA IN
DATA VALID
2967 drw 09
NOTES:
1. A write occurs during the overlap of a LOW WE , a LOW CS 1 and a HIGH CS 2 .
2. t WR1, 2 is measured from the earlier of CS 1 or WE going HIGH or CS 2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS 1 LOW transition or CS 2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ +t DW ) to allow the I/O drivers to
turn off and data to be placed on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified t WP .
6. Transition is measured ±200mV from steady state.
8
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